DDR3 SDRAM

In computing, DDR3 SDRAM, an abridgement for bifold abstracts amount blazon three ancillary activating accidental admission memory, is a avant-garde affectionate of activating accidental admission anamnesis (DRAM) with a top bandwidth interface. It is one of several variants of DRAM and associated interface techniques acclimated back the aboriginal 1970s. DDR3 SDRAM is neither advanced nor astern accordant with any beforehand blazon of accidental admission anamnesis (RAM) due to altered signaling voltages, timings, and added factors.

DDR3 is a DRAM interface specification. The absolute DRAM arrays that abundance the abstracts are agnate to beforehand types, with agnate performance.

The primary account of DDR3 SDRAM over its actual predecessor, DDR2 SDRAM, is its adeptness to alteration abstracts at alert the amount (eight times the acceleration of its centralized anamnesis arrays), enabling college bandwidth or aiguille abstracts rates. With two transfers per aeon of a quadrupled clock, a 64-bit advanced DDR3 bore may accomplish a alteration amount of up to 64 times the anamnesis alarm acceleration in megabytes per additional (MB/s). With abstracts getting transferred 64 $.25 at a time per anamnesis module, DDR3 SDRAM gives a alteration amount of (memory alarm rate) × 4 (for bus alarm multiplier) × 2 (for abstracts rate) × 64 (number of $.25 transferred) / 8 (number of bits/byte). Thus with a anamnesis alarm abundance of 100 MHz, DDR3 SDRAM gives a best alteration amount of 6400 MB/s. In addition, the DDR3 accepted permits dent capacities of up to 8 gigabytes.

Overview

Compared to DDR2 memory, DDR3 anamnesis uses 30% beneath power. This abridgement comes from the aberration in accumulation voltages: 1.8V or 2.5V for DDR2, and 1.5V for DDR3. The 1.5 V accumulation voltage works able-bodied with the 90 nanometer artifact technology acclimated in the aboriginal DDR3 chips. Some manufacturers added adduce application "dual-gate" transistors to abate arising of current.1

According to JEDEC2, 1.575 volts should be advised the complete best if anamnesis adherence is the foremost consideration, such as in servers or added mission-critical devices. In addition, JEDEC states that anamnesis modules accept to bear up to 1.975 volts afore incurring abiding damage, although they are not appropriate to action accurately at that level.

JEDEC alien two low-voltage standards. The DDR3L accepted is 1.35V and has the characterization ’’PC3L’’ for its modules. Examples cover DDR3L‐800, DDR3L‐1066, DDR3L‐1333, and DDR3L‐1600. The DDR3U accepted is 1.25V and has the characterization ’’PC3U’’ for its modules.

The capital account of DDR3 comes from the college bandwidth fabricated accessible by its prefetch buffer, which is 8-burst-deep. In contrast, the prefetch absorber of DDR2 is 4-burst-deep, and the prefetch absorber of DDR is 2-burst-deep.

DDR3 modules can alteration abstracts at a amount of 800–2133 MT/s application both ascent and falling edges of a 400–1066 MHz I/O clock. Sometimes, a bell-ringer may misleadingly acquaint the I/O alarm amount by labeling the MT/s as MHz. The MT/s is commonly alert that of MHz by bifold sampling, one on the ascent alarm edge, and the other, on the falling. In comparison, DDR2's accepted ambit of abstracts alteration ante is 400–1066 MT/s application a 200–533 MHz I/O clock, and DDR's ambit is 200–400 MT/s based on a 100–200 MHz I/O clock. High-performance cartoon was an antecedent disciplinarian of such bandwidth requirements, area top bandwidth abstracts alteration amid framebuffers is required.

DDR3 does use the aforementioned electric signaling accepted as DDR and DDR2, Stub Series Terminated Logic, admitting at altered timings and voltages. Specifically, DDR3 uses SSTL_15.3

DDR3 prototypes were appear in aboriginal 2005. Products in the anatomy of motherboards appeared on the bazaar in June 20074 based on Intel's P35 "Bearlake" chipset with DIMMs at bandwidths up to DDR3-1600 (PC3-12800).5 The Intel Core i7, appear in November 2008, connects anon to anamnesis rather than via a chipset. The Core i7 supports alone DDR3. AMD's aboriginal atrium AM3 Phenom II X4 processors, appear in February 2009, were their aboriginal to abutment DDR3.

DDR3 DIMMs accept 240 pins and are electrically adverse with DDR2. The two are prevented from getting accidentally alternate by altered key cleft positions on the DIMMs.6 DDR3 SO-DIMMs accept 204 pins.7

GDDR3 memory, sometimes afield referred to as "DDR3" due to its agnate name, is an absolutely altered technology, as it is advised for use in cartoon cards and is based on DDR2 SDRAM.

Latencies

While the archetypal latencies for a JEDEC DDR2 accessory were 5-5-5-15, some accepted latencies for JEDEC DDR3 accessories cover 7-7-7-20 for DDR3-1066 and 8-8-8-24 for DDR3-1333.

DDR3 latencies are numerically college because the I/O bus alarm cycles by which they are abstinent are shorter; the absolute time breach is agnate to DDR2 latencies (around 10 ns). There is some advance because DDR3 about uses added contempo accomplishment processes, but this is not anon acquired by the change to DDR3.

As with beforehand anamnesis generations, faster DDR3 anamnesis became accessible afterwards the absolution of the antecedent versions. DDR3-2000 anamnesis with 9-9-9-28 cessation (9 ns) was accessible in time to accompany with the Intel Core i7 release.8 CAS cessation of 9 at 1000 MHz (DDR3-2000) is 9 ns, while CAS cessation of 7 at 667 MHz (DDR3-1333) is 10.5 ns.

(CAS / Frequency (MHz)) × 1000 = X ns

Example:

(7 / 667) × 1000 = 10.4948 ns

Extensions

Intel Corporation clearly alien the eXtreme Memory Profile (XMP) Specification on March 23, 2007 to accredit enthusiast achievement extensions to the acceptable JEDEC SPD blueprint for DDR3 SDRAM.9

Modules

JEDEC accepted modules

Standard name

Memory clock

(MHz)

Cycle time

(ns)

I/O bus clock

(MHz)

Data rate

(MT/s)

Module name

Peak alteration rate

(MB/s)

Timings

(CL-tRCD-tRP)

CAS latency

(ns)

DDR3-800D

DDR3-800E 100 10 400 800 PC3-6400 6400 5-5-5

6-6-6 12 1⁄2

15  

DDR3-1066E

DDR3-1066F

DDR3-1066G 133⅓ 7 1⁄2 533⅓ 1066⅔ PC3-8500 8533⅓ 6-6-6

7-7-7

8-8-8 11 1⁄4

13 1⁄8

15  

DDR3-1333F*

DDR3-1333G

DDR3-1333H

DDR3-1333J* 166⅔ 6 666⅔ 1333⅓ PC3-10600 10666⅔ 7-7-7

8-8-8

9-9-9

10-10-10 10 1⁄2

12  

13 1⁄2

15  

DDR3-1600G*

DDR3-1600H

DDR3-1600J

DDR3-1600K 200 5 800 1600 PC3-12800 12800 8-8-8

9-9-9

10-10-10

11-11-11 10  

11 1⁄4

12 1⁄2

13 3⁄4

DDR3-1866J*

DDR3-1866K

DDR3-1866L

DDR3-1866M* 233⅓ 4 2⁄7 933⅓ 1866⅔ PC3-14900 14933⅓ 10-10-10

11-11-11

12-12-12

13-13-13 10 5⁄7 

11 11⁄14

12 6⁄7 

13 13⁄14

DDR3-2133K*

DDR3-2133L

DDR3-2133M

DDR3-2133N* 266⅔ 3 3⁄4 1066⅔ 2133⅓ PC3-17000 17066⅔ 11-11-11

12-12-12

13-13-13

14-14-14 10 5⁄16

11 1⁄4

12 3⁄16

13 1⁄8

* optional

CL - Alarm cycles amid sending a cavalcade abode to the anamnesis and the alpha of the abstracts in response

tRCD - Alarm cycles amid row actuate and reads/writes

tRP - Alarm cycles amid row precharge and activate

Fractional frequencies are commonly angled down, but rounding up to -667 is accepted due to the exact amount getting -666⅔ and rounding to the abutting accomplished number. Some manufacturers aswell annular to a assertive attention or annular up instead. For example, PC3-10666 anamnesis could be listed as PC3-10600 or PC3-10700.10

Note: All items listed aloft are defined by JEDEC as JESD79-3D.11 All RAM abstracts ante average or aloft these listed blueprint are not connected by JEDEC—often they are artlessly architect optimizations application higher-tolerance or overvolted chips. Of these non-standard specifications, the accomplished appear acceleration accomplished was agnate to DDR3-2544, as of May 2010.12

DDR3-xxx denotes abstracts alteration rate, and describes raw DDR chips, admitting PC3-xxxx denotes abstract bandwidth (with the endure two digits truncated), and is acclimated to call accumulated DIMMs. Bandwidth is affected by demography transfers per added and adding by eight. This is because DDR3 anamnesis modules alteration abstracts on a bus that is 64 abstracts $.25 wide, and back a byte comprises 8 bits, this equates to 8 bytes of abstracts per transfer.

In accession to bandwidth and accommodation variants, modules can

Optionally apparatus ECC, which is an added abstracts byte lane acclimated for acclimation accessory errors and audition above errors for bigger reliability. Modules with ECC are articular by an added ECC or E in their designation. For example: "PC3-6400 ECC", or PC3-8500E.13

Be "registered", which improves arresting candor (and appropriately potentially alarm ante and concrete aperture capacity) by electrically buffering the signals with a register, at a amount of an added alarm of added latency. Those modules are articular by an added R in their designation, admitting non-registered (a.k.a. "unbuffered") RAM may be articular by an added U in the designation. PC3-6400R is a registered PC3-6400 module, and PC3-6400R ECC is the aforementioned bore with ECC.

Be absolutely buffered modules, which are appointed by F or FB and do not accept the aforementioned cleft position as added classes. Absolutely buffered modules cannot be acclimated with motherboards that are fabricated for registered modules, and the altered cleft position physically prevents their insertion.

Feature summary

DDR3 SDRAM components

Introduction of asynchronous RESET pin

Support of system-level flight-time compensation

On-DIMM mirror-friendly DRAM pinout

Introduction of CWL (CAS address latency) per alarm bin

On-die I/O arrangement engine

READ and WRITE calibration

DDR3 modules

Fly-by command/address/control bus with on-DIMM termination

High-precision arrangement resistors

Are not backwards compatible—DDR3 modules do not fit into DDR2 sockets; banishment them can accident the DIMM and/or the motherboard14

Technological advantages compared to DDR2

Higher bandwidth performance, up to 2133 MT/s standardized

Slightly bigger latencies, as abstinent in nanoseconds

Higher achievement at low ability (longer array activity in laptops)

Enhanced low-power features

Development and market penetration

In May 2005, Desi Rhoden, administrator of the JEDEC board amenable for creating the DDR3 standard, declared that DDR3 had been beneath development for "about 3 years".15 DDR3 was launched in 2007, but sales were not accepted to beat DDR2 until the end of 2009, or possibly aboriginal 2010, according to Intel architect Carlos Weissenberg, speaking during the aboriginal allotment of their roll-out in August 2008.16 (The aforementioned timescale for bazaar assimilation had been declared by bazaar intelligence aggregation DRAMeXchange over a year beforehand in April 2007,17 and by Desi Rhoden in 2005.15) The primary active force abaft the added acceptance of DDR3 has been new Core i7 processors from Intel and Phenom II processors from AMD, both of which accept centralized anamnesis controllers: the closing recommends DDR3, the above requires it. IDC declared in January 2009 that DDR3 sales will annual for 29 percent of the absolute DRAM units awash in 2009, ascent to 72% by 2011.18

Successor

JEDEC's planned almsman to DDR3 is DDR4, whose accepted is currently in development.19 The primary allowances of DDR4 compared to DDR3 cover a college ambit of alarm frequencies and abstracts alteration rates20 and decidedly lower voltage. Some manufacturers accept already approved DDR4 chips for testing purposes.21