While the archetypal latencies for a JEDEC DDR2 accessory were 5-5-5-15, some accepted latencies for JEDEC DDR3 accessories cover 7-7-7-20 for DDR3-1066 and 8-8-8-24 for DDR3-1333.
DDR3 latencies are numerically college because the I/O bus alarm cycles by which they are abstinent are shorter; the absolute time breach is agnate to DDR2 latencies (around 10 ns). There is some advance because DDR3 about uses added contempo accomplishment processes, but this is not anon acquired by the change to DDR3.
As with beforehand anamnesis generations, faster DDR3 anamnesis became accessible afterwards the absolution of the antecedent versions. DDR3-2000 anamnesis with 9-9-9-28 cessation (9 ns) was accessible in time to accompany with the Intel Core i7 release.8 CAS cessation of 9 at 1000 MHz (DDR3-2000) is 9 ns, while CAS cessation of 7 at 667 MHz (DDR3-1333) is 10.5 ns.
(CAS / Frequency (MHz)) × 1000 = X ns
Example:
(7 / 667) × 1000 = 10.4948 ns
DDR3 latencies are numerically college because the I/O bus alarm cycles by which they are abstinent are shorter; the absolute time breach is agnate to DDR2 latencies (around 10 ns). There is some advance because DDR3 about uses added contempo accomplishment processes, but this is not anon acquired by the change to DDR3.
As with beforehand anamnesis generations, faster DDR3 anamnesis became accessible afterwards the absolution of the antecedent versions. DDR3-2000 anamnesis with 9-9-9-28 cessation (9 ns) was accessible in time to accompany with the Intel Core i7 release.8 CAS cessation of 9 at 1000 MHz (DDR3-2000) is 9 ns, while CAS cessation of 7 at 667 MHz (DDR3-1333) is 10.5 ns.
(CAS / Frequency (MHz)) × 1000 = X ns
Example:
(7 / 667) × 1000 = 10.4948 ns
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