JEDEC accepted modules
Standard name
Memory clock
(MHz)
Cycle time
(ns)
I/O bus clock
(MHz)
Data rate
(MT/s)
Module name
Peak alteration rate
(MB/s)
Timings
(CL-tRCD-tRP)
CAS latency
(ns)
DDR3-800D
DDR3-800E 100 10 400 800 PC3-6400 6400 5-5-5
6-6-6 12 1⁄2
15
DDR3-1066E
DDR3-1066F
DDR3-1066G 133⅓ 7 1⁄2 533⅓ 1066⅔ PC3-8500 8533⅓ 6-6-6
7-7-7
8-8-8 11 1⁄4
13 1⁄8
15
DDR3-1333F*
DDR3-1333G
DDR3-1333H
DDR3-1333J* 166⅔ 6 666⅔ 1333⅓ PC3-10600 10666⅔ 7-7-7
8-8-8
9-9-9
10-10-10 10 1⁄2
12
13 1⁄2
15
DDR3-1600G*
DDR3-1600H
DDR3-1600J
DDR3-1600K 200 5 800 1600 PC3-12800 12800 8-8-8
9-9-9
10-10-10
11-11-11 10
11 1⁄4
12 1⁄2
13 3⁄4
DDR3-1866J*
DDR3-1866K
DDR3-1866L
DDR3-1866M* 233⅓ 4 2⁄7 933⅓ 1866⅔ PC3-14900 14933⅓ 10-10-10
11-11-11
12-12-12
13-13-13 10 5⁄7
11 11⁄14
12 6⁄7
13 13⁄14
DDR3-2133K*
DDR3-2133L
DDR3-2133M
DDR3-2133N* 266⅔ 3 3⁄4 1066⅔ 2133⅓ PC3-17000 17066⅔ 11-11-11
12-12-12
13-13-13
14-14-14 10 5⁄16
11 1⁄4
12 3⁄16
13 1⁄8
* optional
CL - Alarm cycles amid sending a cavalcade abode to the anamnesis and the alpha of the abstracts in response
tRCD - Alarm cycles amid row actuate and reads/writes
tRP - Alarm cycles amid row precharge and activate
Fractional frequencies are commonly angled down, but rounding up to -667 is accepted due to the exact amount getting -666⅔ and rounding to the abutting accomplished number. Some manufacturers aswell annular to a assertive attention or annular up instead. For example, PC3-10666 anamnesis could be listed as PC3-10600 or PC3-10700.10
Note: All items listed aloft are defined by JEDEC as JESD79-3D.11 All RAM abstracts ante average or aloft these listed blueprint are not connected by JEDEC—often they are artlessly architect optimizations application higher-tolerance or overvolted chips. Of these non-standard specifications, the accomplished appear acceleration accomplished was agnate to DDR3-2544, as of May 2010.12
DDR3-xxx denotes abstracts alteration rate, and describes raw DDR chips, admitting PC3-xxxx denotes abstract bandwidth (with the endure two digits truncated), and is acclimated to call accumulated DIMMs. Bandwidth is affected by demography transfers per added and adding by eight. This is because DDR3 anamnesis modules alteration abstracts on a bus that is 64 abstracts $.25 wide, and back a byte comprises 8 bits, this equates to 8 bytes of abstracts per transfer.
In accession to bandwidth and accommodation variants, modules can
Optionally apparatus ECC, which is an added abstracts byte lane acclimated for acclimation accessory errors and audition above errors for bigger reliability. Modules with ECC are articular by an added ECC or E in their designation. For example: "PC3-6400 ECC", or PC3-8500E.13
Be "registered", which improves arresting candor (and appropriately potentially alarm ante and concrete aperture capacity) by electrically buffering the signals with a register, at a amount of an added alarm of added latency. Those modules are articular by an added R in their designation, admitting non-registered (a.k.a. "unbuffered") RAM may be articular by an added U in the designation. PC3-6400R is a registered PC3-6400 module, and PC3-6400R ECC is the aforementioned bore with ECC.
Be absolutely buffered modules, which are appointed by F or FB and do not accept the aforementioned cleft position as added classes. Absolutely buffered modules cannot be acclimated with motherboards that are fabricated for registered modules, and the altered cleft position physically prevents their insertion.
Standard name
Memory clock
(MHz)
Cycle time
(ns)
I/O bus clock
(MHz)
Data rate
(MT/s)
Module name
Peak alteration rate
(MB/s)
Timings
(CL-tRCD-tRP)
CAS latency
(ns)
DDR3-800D
DDR3-800E 100 10 400 800 PC3-6400 6400 5-5-5
6-6-6 12 1⁄2
15
DDR3-1066E
DDR3-1066F
DDR3-1066G 133⅓ 7 1⁄2 533⅓ 1066⅔ PC3-8500 8533⅓ 6-6-6
7-7-7
8-8-8 11 1⁄4
13 1⁄8
15
DDR3-1333F*
DDR3-1333G
DDR3-1333H
DDR3-1333J* 166⅔ 6 666⅔ 1333⅓ PC3-10600 10666⅔ 7-7-7
8-8-8
9-9-9
10-10-10 10 1⁄2
12
13 1⁄2
15
DDR3-1600G*
DDR3-1600H
DDR3-1600J
DDR3-1600K 200 5 800 1600 PC3-12800 12800 8-8-8
9-9-9
10-10-10
11-11-11 10
11 1⁄4
12 1⁄2
13 3⁄4
DDR3-1866J*
DDR3-1866K
DDR3-1866L
DDR3-1866M* 233⅓ 4 2⁄7 933⅓ 1866⅔ PC3-14900 14933⅓ 10-10-10
11-11-11
12-12-12
13-13-13 10 5⁄7
11 11⁄14
12 6⁄7
13 13⁄14
DDR3-2133K*
DDR3-2133L
DDR3-2133M
DDR3-2133N* 266⅔ 3 3⁄4 1066⅔ 2133⅓ PC3-17000 17066⅔ 11-11-11
12-12-12
13-13-13
14-14-14 10 5⁄16
11 1⁄4
12 3⁄16
13 1⁄8
* optional
CL - Alarm cycles amid sending a cavalcade abode to the anamnesis and the alpha of the abstracts in response
tRCD - Alarm cycles amid row actuate and reads/writes
tRP - Alarm cycles amid row precharge and activate
Fractional frequencies are commonly angled down, but rounding up to -667 is accepted due to the exact amount getting -666⅔ and rounding to the abutting accomplished number. Some manufacturers aswell annular to a assertive attention or annular up instead. For example, PC3-10666 anamnesis could be listed as PC3-10600 or PC3-10700.10
Note: All items listed aloft are defined by JEDEC as JESD79-3D.11 All RAM abstracts ante average or aloft these listed blueprint are not connected by JEDEC—often they are artlessly architect optimizations application higher-tolerance or overvolted chips. Of these non-standard specifications, the accomplished appear acceleration accomplished was agnate to DDR3-2544, as of May 2010.12
DDR3-xxx denotes abstracts alteration rate, and describes raw DDR chips, admitting PC3-xxxx denotes abstract bandwidth (with the endure two digits truncated), and is acclimated to call accumulated DIMMs. Bandwidth is affected by demography transfers per added and adding by eight. This is because DDR3 anamnesis modules alteration abstracts on a bus that is 64 abstracts $.25 wide, and back a byte comprises 8 bits, this equates to 8 bytes of abstracts per transfer.
In accession to bandwidth and accommodation variants, modules can
Optionally apparatus ECC, which is an added abstracts byte lane acclimated for acclimation accessory errors and audition above errors for bigger reliability. Modules with ECC are articular by an added ECC or E in their designation. For example: "PC3-6400 ECC", or PC3-8500E.13
Be "registered", which improves arresting candor (and appropriately potentially alarm ante and concrete aperture capacity) by electrically buffering the signals with a register, at a amount of an added alarm of added latency. Those modules are articular by an added R in their designation, admitting non-registered (a.k.a. "unbuffered") RAM may be articular by an added U in the designation. PC3-6400R is a registered PC3-6400 module, and PC3-6400R ECC is the aforementioned bore with ECC.
Be absolutely buffered modules, which are appointed by F or FB and do not accept the aforementioned cleft position as added classes. Absolutely buffered modules cannot be acclimated with motherboards that are fabricated for registered modules, and the altered cleft position physically prevents their insertion.
No comments:
Post a Comment